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New PDF release: Analog Design Issues in Digital VLSI Circuits and Systems: A

By Juan J. Becerra, Eby G. Friedman

ISBN-10: 1461377951

ISBN-13: 9781461377955

ISBN-10: 1461561019

ISBN-13: 9781461561019

Analog layout matters in electronic VLSI Circuits and Systems brings jointly in a single position vital contributions and up to date examine leads to this fast-paced region.
Analog layout concerns in electronic VLSI Circuits and Systems serves as an exceptional reference, supplying perception into probably the most tough study matters within the field.

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Extra resources for Analog Design Issues in Digital VLSI Circuits and Systems: A Special Issue of Analog Integrated Circuits and Signal Processing, An International Journal Volume 14, Nos. 1/2 (1997)

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The excess current dissipated during this region is called the short-circuit (or crossover) current [16]. Short-circuit current occurs due to a slow input transition, and for a balanced inverter, the peak current occurs near the middle of the input transition. , the SPICE-derived data. The total short-circuit current I sc can be estimated by modeling 1sc as a triangle. Therefore, the integral of lsc is the area of a triangle, ~base x height. In terms of the short-circuit current, the height can be modeled as I peak and the base can be modeled as tbase (see Figure 5).

Adler and E. Friedman 4. M. Nekili and Y. Savaria, "Optimal Methods of Driving Interconnections in VLSI Circuits," Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 21-23, May 1992. 5. C. Y. Wu and M. Shiau, "Delay Models and Speed Improvement Techniques for RC Tree Interconnections Among SmallGeometry CMOS Inverters," IEEE Journal of Solid-State Circuits SC-25(5), pp. 1247-1256, October 1990. 6. J. -K. Koh, "Simultaneous Driver and Wire Sizing for Performance and Power Optimization," IEEE Transactions on VLSI Systems VLSI-2(4), pp.

Delay and Power Expressions Assuming a unit step input is applied to the circuit shown in Figure 1, Vout SCVout + S'UdoRCVout + Udo Vaut = CVaur(O) + UdoRCVaur(O), (3) where Udo = #uis the saturation conductance. •do Equation (3) yields (4) Graphs of V0 u1 (t) for a wide range of resistive and capacitive values (within practical limits) are shown in Figure 3. The analytical expression shown in (4) closely approximates SPICE for most of the region of operation for a wide range of load impedances from 10 Q to 1000 Q and from 10 fF to 1 pF.

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Analog Design Issues in Digital VLSI Circuits and Systems: A Special Issue of Analog Integrated Circuits and Signal Processing, An International Journal Volume 14, Nos. 1/2 (1997) by Juan J. Becerra, Eby G. Friedman


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